doc.# dsfp-vn2222ll b082013 vn2222ll yy = year sealed ww = week sealed = ?green? packaging si vn 2222l l yyww features ? free from secondary breakdown ? low power drive requirement ? ease of paralleling ? low c iss and fast switching speeds ? excellent thermal stability ? integral source-drain diode ? high input impedance and high gain applications ? motor controls ? converters ? amplifers ? switches ? power supply circuits ? drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) general description this e nhancement-mode (normally-off) transistor utilizes a vertical dmos structure and supertexs well-proven, silicon-gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coeffcient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally-induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. n-channel enhancement-mode vertical dmos fet absolute maximum ratings parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 30v operating and storage temperature -55 o c to +150 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. to-92 product marking package may or may not include the following marks: si or pin confguration to-92 gate source drain product summary bv dss /bv dgs r ds(on) (max) i d(on) (min) 60v 7.5 750ma typical thermal resistance package ja to-92 132 o c/w ordering information part number package option packing vn2222ll-g to-92 1000/bag vn2222ll-g p002 to-92 2000/reel vn2222ll-g p003 vn2222ll-g p005 vn2222ll-g p013 vn2222ll-g p014 -g denotes a lead (pb)-free / rohs compliant package. contact factory for wafer / die availablity. devices in wafer / die form are lead (pb)-free / rohs compliant. supertex inc. supertex inc. www .supertex.com
2 doc.# dsfp-vn2222ll b082013 vn2222ll electrical characteristics (t a = 25c unless otherwise specifed) sym parameter min typ max units conditions bv dss drain-to-source breakdown voltage 60 - - v v gs = 0v, i d = 100a v gs(th) gate threshold voltage 0.6 - 2.5 v v gs = v ds , i d = 1.0ma i gss gate body leakage current - - 100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current - - 10 a v gs = 0v, v ds = max rating - - 500 v gs = 0v, v ds = 48v, t a = 125 o c i d(on) on-state drain current 0.75 - - a v gs = 10v, v ds = 10v r ds(on) static drain-to-source on-state resistance - - 7.5 v gs = 5.0v, i d = 200ma - - 7.5 v gs = 10v, i d = 500ma g fs forward transconductance 100 - - mmho v ds = 10v, i d = 500ma c iss input capacitance - - 60 pf v gs = 0v, v ds = 25v, f = 1.0mhz c oss common source output capacitance - - 25 c rss reverse transfer capacitance - - 8.0 t (on) turn-on time - - 10 ns v dd = 15v, i d = 0.6a, r gen = 25? t (off) turn-off time - - 10 v sd diode forward voltage drop - 0.85 - v v gs = 0v, i sd = 0.2a notes: 1. all d.c. parameters 100% tested at 25 o c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator vdd r l output d.u.t. t (on) t d(on) t (off) t d(off) t r input input output 10v vdd r gen 0v 0v t f notes: ? i d (continuous) is limited by max rated t j . thermal characteristics package i d (continuous) ? i d (pulsed) power dissipation @t c = 25 o c i dr ? i drm to-92 230ma 1.0a 1.0w 230ma 1.0a supertex inc. www .supertex.com
3 vn2222ll (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-vn2222ll b082013 3-lead to-92 package outline (ll) symbol a b c d e e1 e e1 l dimensions (inches) min .170 .014 ? .014 ? .175 .125 .080 .095 .045 .500 nom - - - - - - - - - max .210 .022 ? .022 ? .205 .165 .105 .105 .055 .610* jedec registration to-92. * this dimension is not specifed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc.#: dspd-3to92n3, version e041009. seating plane 1 2 3 front v iew side v iew bottom v iew e1 e d e1 l e c 1 2 3 b a supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
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